1. Field of the Invention
The present invention relates to the structure of an insulated gate semiconductor device formed using a crystalline by semiconductor substrate, for example, a monocrystal silicon substrate or an SOI substrate (SIMOX or the like), and more particularly to the structure of an insulated gate field effect transistor (hereinafter referred to simply as xe2x80x9cIG-FETxe2x80x9d) and a method of manufacturing the same. The present invention relates to a technique of which advantages are especially exhibited in the case of manufacturing a fine device whose channel length is 1 xcexcm or less (representatively, 0.01 to 0.35 xcexcm).
Therefore, the present invention is applicable to a semiconductor integrated circuit such as an IC, a VLSI or a ULSI, which is structured with integrated IG-FETs.
2. Description of the Related Art
In recent years, integrated circuits such as the VLSI are kept on becoming more fine, and the machining dimensions in the order of a deep sub-micron are required, for example, the width of a wiring is 0.18 xcexcm or less, further 0.1 xcexcm or less.
Up to now, the fining of a semiconductor device is progressed in accordance with the scaling rule, and there has been generally known that the fining leads to an improvement in the characteristic of the integrated circuit. However, the fine machining in the order of the sub-micron suffers from a problem that it does not simply accord to the scaling rule.
The representative problem of this type as known is a phenomenon such as a short channel effect. The short channel effect is the phenomenon caused by the reason that as the line width of a gate electrode is shortened, that is, a channel formation region is shortened the charges in the channel formation region becomes to be largely influenced by not only a gate voltage but also the charges in a depletion layer, an electric field and a potential distribution of a source/drain region.
This state is simplified and shown in FIG. 3. Reference numeral 301 denotes a source region, reference numeral 302 denotes a drain region, reference numeral 303 denotes a channel region, and reference numeral 304 denotes a gate electrode. Also, a dotted line indicated by reference numeral 305 represents a depletion layer which is formed when a drain voltage Vd is small.
Normally, a current that flows in the channel region 303 is controlled by only a gate voltage Vg. In this case, as indicated by reference numeral 305, since the depletion layer which is in the vicinity of the channel region 303 is substantially in parallel with the channel, a uniform electric field is formed.
However, as the drain voltage Vd becomes high, the depletion layer which is in the vicinity of the drain region 302 is expanded toward the channel region 303 and the source region 301, with the result that as indicated by a solid line 306, the charge and the electric field in the drain depletion layer become to influence the depletion layer which is in the vicinity of the source region 301 and the channel region 303. In other words, an on-state current is changed according to a complicated electric field distribution, thereby making it difficult to control the current which flows in the channel region 303 by only the gate voltage Vg.
Here, an energy state in the periphery of the channel formation region when the short channel effect occurs will be described with reference to FIG. 4. In FIG. 4, state graphs indicated by solid lines represent energy bands of the source region 401, the channel formation region 402 and the drain region 403, respectively, when the drain voltage is 0 V.
In this state, when the drain voltage Vd which is sufficiently large is applied, the energy bands are changed into the states indicated by dotted lines in FIG. 4. In other words, the depletion charges and the electric field in the drain region 103 which are formed by the drain voltage Vd influence the charges in the depletion layers of the source and channel regions 401 and 402 so that an energy (potential) state is continuously changed from the source region 401 to the drain region 403.
The deterioration of a threshold value voltage (Vth) and a punch-through phenomenon have been well known as an influence of such a short channel effect on the semiconductor device, for example, the IG-FET. Also, there has been known that a sub-threshold characteristic is deteriorated when an influence of the gate voltage on the drain current by the punch-through phenomenon is lowered.
First, the deterioration of the threshold value voltage is a phenomenon that occurs in an n-channel FET and a p-channel FET, similarly. Also, the degree of the deterioration depends on not only the drain voltage but also a variety of parameters such as the concentration of impurities in a substrate, the depth of source/drain diffusion layer, the thickness of a gate oxide film, a substrate bias and so on.
The deterioration of the threshold value voltage is desirable from a viewpoint of lowering a power consumption, however, there generally arises such a disadvantage that a frequency characteristic is not increased because the drive voltage of the integrate circuit becomes small.
Under that circumstance, up to now, as means for controlling the threshold value voltage, it is general to uniformly add the impurity elements that give one conduction to the entire channel formation region, to control the threshold value voltage with the amount of addition of the impurity elements. However, even with this method, the short channel effect per se cannot be prevented, and the punch-through phenomenon is caused to occur. Also, since the added impurities allow carriers to be scattered, the mobility of carriers is caused to be lowered.
Also, the deterioration of the sub-threshold characteristic which is accompanied by the punch-through phenomenon means that the sub-threshold coefficient (S value) is increased, that is, the switching characteristic of an FET is deteriorated. An influence of the short channel effect on the sub-threshold characteristic is shown in FIG. 5.
FIG. 5 is a graph taking the gate voltage Vg in a horizontal axis and the logarithm of the drain current Id in a vertical axis. The inverse number of a slope (sub-threshold characteristic) in the region 501 is an S value. In FIG. 5, the changes of characteristics when gradually shortening the channel length are compared, and the channel length is shortened toward a direction indicated by an arrow.
As a result, there can be confirmed that the slope of the characteristic is decreased, that is, the S value is tended to be increased with the channel length being shortened. This means that the switching characteristic of the FET is deteriorated with the channel length being shortened.
The above-description is made to the short channel effect in the case of extremely shortening the length of the channel formation region of the semiconductor device. In the case of extremely narrowing the width of the channel formation region, the phenomenon such as the narrow channel effect also occurs.
What is shown in FIG. 6 is a cross-sectional view showing a normal IG-FET being cut on a plane perpendicular to the channel direction (a direction connecting the source and, the drain). Reference numeral 601 denotes a monocrystal silicon substrate, and reference numeral 602 denotes a field oxide film formed through the selectively oxidizing method. The respective semiconductor devices used in the VLSI are separated by the field oxide film 602, respectively.
Also, reference numeral 603 denotes a gate electrode to which a voltage is applied to form a channel region 604. Impurity region 605 is disposed below the field oxide film 602 and functions as a channel stopper.
The narrow channel effect is caused in such a manner that a bird beak portion is largely influenced which is an intrusion of the field oxide film 602 and the impurity region 605 into the channel region 604 is largely influenced as the channel width W is narrowed. In particular, there may be cited an increase in the threshold value voltage and a dependency of the effective channel width on a supply voltage.
In the existing semiconductor industry, a semiconductor integrated circuit which has been integrated up to the limit has been demanded, and it is important to which degree the fining of the respective semiconductor devices can be pursued. However, even if a technique to form a fine pattern in the order of the deep sub-micron is formed is developed, the problem of the above-mentioned short channel effect leads to a fatal obstacle that obstructs the fining of the device.
The present invention has been made in view of the above circumstances, and therefore an object of the present invention is to provide a technique for effectively restraining the short channel effect accompanied by the fining of the semiconductor device, thereby being capable of forming the fine device in the order of the deep sub-micron which was difficult to realize by the short channel effect.
One structure of the present invention as described in the present specification is featured by comprising:
a source region, a drain region and a channel forming region which are formed using a crystal semiconductor;
an impurity region artificially and locally in said channel forming region; and
a gate insulating film and a gate electrode formed on said channel forming region;
wherein impurity elements that shift an energy band width (Eg) are added to said impurity region, and a path in which carriers move is controlled by said impurity region.
Also, another structure of the invention is featured by comprising:
a source region, a drain region and a channel forming region which are formed using a crystal semiconductor; and
a gate insulating film and a gate electrode formed on said channel forming region;
wherein said channel forming region includes a region in which carriers move, and an impurity region which pins a depletion layer that expands from said drain region toward said channel forming region and said source region and which is artificially and locally formed to control a path through which the carriers move; and
wherein impurity elements that shift an energy band width (Eg) are added to said impurity region.
Further, another structure of the invention is featured by comprising:
a source region, a drain region and a channel forming region which are formed using a crystal semiconductor; and
a gate insulating film and a gate electrode formed on said channel forming region;
wherein said channel forming region includes a region in which carriers move, and an impurity region which pins a depletion layer that expands from said drain region toward said channel forming region and said source region and which is artificially and locally formed to control a path through which the carriers move;
wherein impurity elements that shift an energy band width (Eg) are added to said impurity region; and
wherein said region in which the carriers move includes means for preventing the impurity scattering of the carriers or means for preventing the deterioration of the mobility which is caused by a factor other than the scattering of a lattice of the carriers.
Yet still further, another structure of the invention is featured by comprising:
a source region, a drain region and a channel forming region which are formed using a crystal semiconductor; and
a gate insulating film and a gate electrode formed on said channel forming region;
wherein said channel forming region includes a region in which carriers move, and an impurity region which is controlled to a predetermined value voltage by the addition of impurity elements and artificially and locally formed to control a path through which the carriers move; and
wherein impurity elements that shift an energy band width (Eg) are added to said impurity region.
Further, another structure of the invention is featured by comprising:
a source region, a drain region and a channel forming region which are formed using a crystal semiconductor; and
a gate insulating film and a gate electrode formed on said channel forming region;
wherein said channel forming region includes a region in which carriers move, and an impurity region which is controlled to a predetermined value voltage by the addition of impurity elements and artificially and locally formed to control a path through which the carriers move;
wherein impurity elements that shift an energy band width (Eg) are added to said impurity region; and
wherein said region in which the carriers move includes means for preventing the impurity scattering of the carriers or means for preventing the deterioration of the mobility which is caused by a factor other than the scattering of a lattice of the carriers.
Further, still another structure of the invention is featured by comprising:
a source region, a drain region and a channel forming region which are formed using a crystal semiconductor;
an impurity region artificially and locally in said channel forming region by addition of impurity elements that shift an energy band width (Eg) in said channel forming region; and
a gate insulating film and a gate electrode formed on said channel forming region;
wherein said impurity region has an insulating property;
wherein a path in which carriers move is controlled by said impurity region; and
wherein said impurity elements are not added or are added by a very small amount in a region other than said impurity region in said channel forming region.
It should be noted that no addition of impurity elements in a region other than the impurity region or a small amount of addition thereof means that a region (semiconductor layer) where a channel is formed is an intrinsic or substantially intrinsic region.
In the present specification, the intrinsic region is directed to a region to which impurity elements that give n-type or p-type and impurity elements such as carbon, nitrogen or oxygen are not intentionally added. Also, the substantially intrinsic region is directed to a region in which a conductive type which is caused even if impurity elements that give n-type or p-type are not intentionally added is offset, or a region that has the same conductive type as that of the source and drain regions in a range where the threshold value can be controlled.
Also, in the present specification, the intrinsic or the substantially intrinsic region is directed to a region where the concentration of phosphorus or boron is 5xc3x971017 atms/cm3 or less, and the concentration of carbon, nitrogen or oxygen is 2xc3x971018 atms/cm3 or less.
Also, in the present invention, as the above impurity elements, there may be used elements of group XIII (representatively boron) which can function as an acceptor that gives p-type conduction with respect to the n-channel FET. Further, there may be elements of group XV (representatively phosphorus and arsenic) which can function as a donor that gives n-type conduction with respect to the p-channel FET.
The impurity region added with these impurity elements function to change the energy band configuration of the channel region and to either increase or reduce the threshold voltage. Accordingly, the concentration of the added impurity in the impurity region should be sufficiently high to at least control the threshold voltage, for example, 1xc3x971017 to 1xc3x971020 atoms/cm3, preferably, 1xc3x971018 to 1xc3x971019 atoms/cm3.
The concentration of the impurity should be at least 100 times as high as the impurity concentration of the substrate (in a typical single crystal silicon substrate, it is about 1xc3x971015/cm3), hence, 1xc3x971017/cm3 is the lower limit. Also, if the concentration exceeds 1xc3x971020 atoms/cm3, it is not desirable in view of the burden of the device.
In the present specification, monocrystal silicon is a representative example of a crystal semiconductor, and the monocrystal silicon includes not only a monocrystal silicon with a grade which is normally used in the level of the current VLSI, but also monocrystal silicon with a higher grade (to the extreme, monocrystal silicon of an ideal state such that it is fabricated in a universal space).
The subject matter of the present invention is to effectively restrain the expansion of a drain depletion layer by an impurity region which is artificially and locally formed from one end (for example, a source region) of the channel formation region toward the other end thereof (for example, a drain region) and substantially in parallel with a channel direction (electric field direction), thereby preventing the punch-through phenomenon and the deterioration of the sub-threshold characteristic accompanied by that phenomenon which are problems in the prior art.
Since the IG-FET of the present invention looks like as if pins of an impurity region are formed in the channel forming region, the present applicant calls it xe2x80x9cpining type transistorxe2x80x9d. In the present specification, xe2x80x9cpiningxe2x80x9d means xe2x80x9crestraintxe2x80x9d, and xe2x80x9cto pinxe2x80x9d means xe2x80x9cto restrainxe2x80x9d or xe2x80x9cto suppressxe2x80x9d.
Also, another subject matter of the present invention is to release by artificially producing the narrow channel effect the deterioration of the threshold value voltage which is a representative phenomenon caused by the short channel effect accompanied by the fining of the channel length is
What is shown in FIG. 1A is a schematic diagram showing states of a source region, a drain region and a channel forming region of a normal IG-FET when being viewed from, a top surface thereof. Reference numeral 101 denotes a source region, reference numeral 102 denotes a drain region, and reference numeral 103 denotes a channel forming region.
The feature of the present invention resides in that an impurity region 104 is formed in the channel region, which has an elongated shape substantially in parallel with the direction of an electric field from one end toward the other end (for example, from the source region 101 toward the drain region 102). In the present invention, as the impurities to be added, n-type impurity such as phosphorus (P) or arsenic (AS) is used with respect to the p-channel FET whereas p-type impurity such as boron (B) is used with respect to the n-channel FET.
The added impurities form an energy barrier which is locally large in an energy band width within the channel forming region 103. For example, in the case where boron (B) that gives p-type conduction is added with respect to the n-channel FET, an energy band which has been in a state shown in FIG. 15A is changed to a state shown in FIG. 15B, and Fermi level (Ef) is shifted whereby a barrier xcex94E becomes a larger barrier xcex94Exe2x80x2. It is needless to say that in this case, the shifting of the Fermi level results in the shifting of an energy band in the channel forming region.
This region has an inverse conductivity and provides a satisfactory barrier from the energy viewpoint though its resistance is low. Likewise, in the case where phosphorus or arsenic is added with respect to the p-channel FET, an inverse conductive region is formed so that it can be applied as an energy barrier.
In particular, as shown in FIG. 1A, since the junction region of the drain region 102 and the channel forming region 103 is a region where an electric field is most remarkably changed, it is desirable that the impurity region 104 is disposed at this position. Also, in the case where an electric field caused by the gate electrode reaches the inside of the drain region 102, the impurity region 104 may extend into the drain region 102. Reversely, it is preferable that no impurity region 104 is formed within the source region 101.
Since these impurities combine firmly with the silicon atoms of the substrate, it is unlikely that these impurities rediffuse during a heat treatment.
Further, the present invention is extremely effective in forming a fine device that requires the fine machining in the order of the deep sub-micron such as a size of 0.2 xcexcm, further 0.1 xcexcm, because the length of the channel forming region (the channel length or a distance between the source and the drain) is also shortened to 0.01 to 1.0 xcexcm, representatively, 0.1 to 0.35 xcexcm, the impurity region must be cut into a finer pattern.
For example, in the case of employing a resist mask in formation of the impurity region which is shaped in a linear pattern, a normal light exposing method cannot be used in a pattering process for defining holes in the resist mask from the viewpoint of a problem on resolution. In such a case, patterning may be performed by using an electron drawing method or an FIB method to realize a fine pattern.
Also, since the linear-pattern shaped impurity region is formed to be artificially arranged by patterning, it can be arranged not only as shown in FIG. 1A but also arbitrarily variously arranged.
Then, a description will be given hereinafter of how to restrain the short channel effect in driving an insulated gate semiconductor device (IG-FET) having the structure of the source region/channel forming region/drain region shown in FIG. 1A.
First, a cross-sectional view taken along a line Axe2x80x94Axe2x80x2 of FIG. 1A is shown in FIG. 1B. Reference numeral 105 denotes a field oxide film, and reference numeral 106 denotes a channel stopper. Since the impurity regions 104 are formed to bridge the source region 101 and the drain region 102, the impurity regions 104 appear without any interruption in a section taken along a line Axe2x80x94Axe2x80x2 as shown in FIG. 1B.
Also, a cross-sectional view taken along a line Bxe2x80x94Bxe2x80x2 of FIG. 1A is shown in FIG. 1C. Reference numeral 107 denotes a field oxide film. Although a depthwise shape of the impurity regions 104 is variable by setting the conditions, this example shows an example in which the impurity regions 104 are in the form of a bar assuming that there is ideally no scattering.
The width of the impurity region 104 is indicated by Wpi,n, and its interval is indicated by Wpa,m. In this example, n and m means that within the channel forming region 103, Wpi, n is a width of the n-th impurity region, and Wpa,m is an interval between the m-th impurity regions (path through which carriers travel).
The above description was made simply to the structure, and its effect will be now described. First, in the case of applying a gate voltage and a drain voltage to a semiconductor device having a structure shown in FIG. 1B, a source side depletion layer 201, a channel side depletion layer 202 and a drain side depletion layer 203 are formed in a state shown in FIG. 2A. In other words, the drain side depletion layer 203 is prevented from expanding toward the source side by an impurity region 204 as a barrier.
Since the impurity region 204 (104) is disposed as shown in FIG. 1A, a model in which a lattice filter that blocks the channel forming region restrains the expansion of the drain side depletion layer facilitates the understanding of the present invention.
Hence, in the semiconductor device having the structure according to the present invention, as shown in FIG. 2A, the depletion layers are divided without being interfered with each other. In other words, since the source side depletion layer 201 and the channel side depletion layer 202 are distributed without being influenced by the drain side depletion layer 203, the energy state becomes a state shown in FIG. 2B.
In other words, since the energy state of the channel region is almost controlled by only an electric field caused by the gate voltage, which is different from the conventional energy state shown in FIG. 5, it has a substantially parallel shape with respect to the channel region. Therefore, with this structure, there arises no problem such as the punch-through phenomenon inherent to the short channel effect, thereby being capable of structuring a semiconductor device high in drain withstand voltage.
Furthermore, as shown in FIG. 2A, in the present invention, because a volume that occupies the depletion layer is reduced in comparison with the prior art shown in FIG. 3, the present invention has the feature that the charges of the depletion layer are smaller than those of the prior art, and that a capacitor in the depletion layer is small. In this example, an expression that leads an S value is represented by the following expression.
S=d(Vg)/d(log 1d)xe2x80x83xe2x80x83[Expression 3]
Namely, as described above, it is understandable that the expression represents the inverse number of a slope in the region 501 in the graph shown in FIG. 5. Also, Expression 3 can be approximately represented by the following expression.
Sxe2x89xa11n10kT/q[1+(Cd+Cit)/Cox]xe2x80x83xe2x80x83[Expression 4]
In Expression 4, k is the Boltzmann""s constant, T is an absolute temperature, q is the amount of charges, Cd is a capacity of the depletion layer, Cit is an equivalent capacity of an interfacial level, and Cox is a capacity of the gate oxide film. Hence, according to the present invention, since the capacity Cd of the depletion layer is sufficiently smaller than that of the prior art, the S value can be set to a small value of 85 mV/decade or less (preferably, 70 mV/decade or less), that is, an excellent sub-threshold characteristic can be obtained.
Also, the object of the present invention is to allow the capacity Cd of the depletion layer and the equivalent capacity Cit of the interfacial level to approach 0 as much as possible. In other words, they are allowed to approach an S value (60 mV/decade) in an ideal state of Cd=Cit=0.
Further, it is very important that the channel forming region is structured as shown in FIG. 1C for releasing the deterioration of the threshold value voltage which is caused by the short channel effect. This is because the structure shown in FIG. 1C is a structure necessary for intentionally producing a narrow channel effect.
For example, when attention is paid to a cross section shown in FIG. 1C, the width W of the channel forming region is divided by the impurity region 104 so that it can be substantially regarded as an assembly consisting of a plurality of channel forming regions having a narrow channel width Wpa,m.
Namely, the narrow channel effect can be obtained in the plurality of regions having the narrow channel width Wpa,m. From the macro viewpoint, since the region where the narrow channel effect thus exists in the entire channel forming region as shown in FIG. 1A, it is considered that the narrow channel effect can be obtained as a whole, thus increasing the threshold value voltage.
Hence, even if the threshold value voltage is lowered by the short channel effect which is caused by shortening the channel length, the threshold value voltage is intentionally increased by the narrow channel effect so that the threshold value voltage can be controlled for the above reason, as a result of which a change in the threshold value voltage can be released.
Also, a method of manufacturing an insulated gate semiconductor device in accordance with another aspect of the invention comprises steps of:
forming a source region, a drain region and a channel forming region using a crystal semiconductor;
forming an impurity region artificially and locally in said channel forming region; and
forming a gate insulating film and a gate electrode on said channel forming region;
wherein impurity elements that shift an energy band width (Eg) are artificially and locally added to said impurity region, and a path in which carriers move is controlled by said impurity region.
Further, a method of manufacturing an insulated gate semiconductor device in accordance with still another aspect of the invention comprises steps of:
forming a source region, a drain region and a channel forming region using a crystal semiconductor;
forming a gate insulating film and a gate electrode on said channel forming region; and
in order to form an impurity region which pins a depletion layer that expands from said drain region toward said channel forming region and said source region and controls a path through which the carriers move, artificially and locally adding impurity elements that shift an energy band width (Eg) to said channel forming region.
A method of manufacturing an insulated gate semiconductor device in accordance with yet another aspect of the invention comprises steps of:
forming a source region, a drain region and a channel forming region using a crystal semiconductor;
forming a gate insulating film and a gate electrode on said channel forming region;
in order to form an impurity region which is controlled to a predetermined threshold value voltage by addition of impurity elements and control a path through which the carriers move, artificially and locally adding impurity elements that shift an energy band width (Eg) to said channel forming region.
A method of manufacturing an insulated gate semiconductor device in accordance with yet still another aspect of the invention comprises steps of:
forming a source region, a drain region and a channel forming region using a crystal semiconductor; and
artificially and locally forming an impurity region by addition of impurity elements that shift an energy band width (Eg) in said channel forming region; and
forming a gate insulating film and a gate electrode formed on said channel forming region;
wherein said impurity region has an insulating property;
wherein a path through which carriers move is controlled by said impurity region; and
wherein said impurity elements are not added or are added by a very small amount in a region other than said impurity region in said channel forming region.